Sr. Asic Design Verification Engineer
Contract to Hire
On-site Milpitas, CA.
In this role, you will work with top-tier DSP, system, and software engineers to define verification strategies and execute plans at both system and full-chip levels. You will be responsible for building and continuously improving verification infrastructure and methodologies to meet the demands of next-generation SoCs. This position offers the opportunity to collaborate closely with system architects, RTL designers, FPGA, and emulation engineers to ensure verification requirements and coverage are met for each project.
Key Responsibilities:
- Define and execute verification strategies at the system or full-chip level.
- Build and continuously improve verification infrastructure and methodologies.
- Collaborate with system architects, RTL designers, FPGA, and emulation engineers.
- Ensure verification requirements and coverage are met for each project.
Requirements:
- Extensive experience with System Verilog, UVM, and C/C++.
- Strong background in building abstraction layered and reusable verification testbench infrastructure.
- Working knowledge of scripting languages such as Python.
- Proven ability to handle complex and challenging problems in programming and verification.
- Excellent interpersonal skills and a collaborative mindset.
Preferred Qualifications:
- Ambitious and dedicated with a strong work ethic.
- Experience in the semiconductor industry, particularly with SoC verification.
- Familiarity with DSP and system-level design verification.
Ways to Stand Out from the Crowd:
- Demonstrated ability to handle complex and hard-to-solve problems in programming and verification.
- Ambitious and dedicated attitude towards work.
- Excellent interpersonal skills for effective collaboration.
- Solid knowledge and strong experience with System Verilog, UVM, and C/C++.
- Proven experience with building abstraction layered and reusable verification testbench infrastructure.
- Proficiency in scripting languages such as Python.
Job Types: Full-time, Contract
Pay: $120.00 - $150.00 per hour
Schedule:
Experience:
- System Verilog: 6 years (Preferred)
- C/C++: 6 years (Preferred)
- UVM: 6 years (Preferred)
Ability to Commute:
Ability to Relocate:
- Milpitas, CA: Relocate before starting work (Required)
Work Location: In person